Metal-oxide-semiconductor (MOS) is a dominating technology for integrated circuits at 90 nm technology and beyond. A MOS device can work in three regions, depending on gate voltage Vg and source-drain voltage Vds, linear, saturation, and sub-threshold regions. The sub-threshold region is a region where the gate voltage Vg is smaller than the threshold voltage Vt. The sub-threshold swing represents the easiness of switching the transistor current off and thus is an important factor in determining the speed and power of a MOS device. The sub-threshold swing can be expressed as a function of m*kT/q, where m is a parameter related to capacitance. The sub-threshold swing of a conventional MOS device has a limit of about 60 mV/decade (kT/q) at room temperature, which in turn sets a limit for further scaling of operation voltage VDD and threshold voltage Vt. This limitation is due to the drift-diffusion transport mechanism of carriers. For this reason, existing MOS devices typically cannot switch faster than 60 mV/decade at room temperature. The 60 mV/decade sub-threshold swing limit also applies to FinFET or ultra thin-body MOSFET on silicon-on-insulator (SOI) devices. However, even with better gate control over the channel, an ultra thin-body MOSFET on SOI or FinFET device can only achieve close to, but not below, the limit of 60 mV/decade. With such a limit, faster switching at low operation voltages for future nanometer devices cannot be achieved.
To solve the above-discussed problem, tunnel field-effect transistors (FETs) have been explored. FIG. 1A illustrates a conventional FET device with gate dielectric 166, gate electrode 168, a heavily doped p-type drain region 164, and a heavily doped n-type source region 162. Drain region 164 is formed by implanting a p-type impurity, while source region 162 is formed by recessing the substrate 163, and epitaxially growing a semiconductor material, followed by doping the semiconductor material with an n-type impurity.
FIG. 1B illustrates an asymmetric tunnel FET device, which includes a heavily doped drain region 202 and a heavily doped source region 204 separated by channel region 203. Drain region 202 comprises silicon, while source region 204 comprises silicon germanium. Channel region 203 is formed of intrinsic silicon. Gate 208 controls channel region 203. The tunnel FET device shown in FIG. 1B has a kT/q independent sub-threshold swing and a low off-state current. However, such a structure can only improve the on-currents of n-channel tunnel FET devices, while the on-currents of p-channel tunnel FET devices are not improved.
The above-mentioned tunnel FET devices suffer from drawbacks. First, they still suffer from gate leakage currents. The gate leakage currents, which are portions of the off-currents of the respective tunnel FETs, limit the further reduction in off-currents when integrated circuits are scaled down. Further, the on-currents of the tunnel FETs are still not high enough to meet demanding technology requirements.
Therefore, the existing tunnel FETs are not suitable for being used in applications requiring very low power consumption and very high speed, such as mobile applications. What is needed in the art, therefore, is a method for further improving the on-currents and reducing leakage currents of MOSFETs.